Cyclone10LP FPGA读写DS1302 RTC实验Verilog逻辑源码Quartus17.1工程文件+文档资料, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 通过分析 DS1302 读写时序，可以看出和 SPI 时序类似，只丌过数据输出和输入分时复用了， 本实验利用 SPI Flash 读写实验中已经使用过的 SPI Master 模块来做为 DS1302 的底层读写控制模块， 然后再编写一个 RTC 读写模块。 ds1302_io 模块完成 DS1302 寄存器读写控制，状态机如下图所示。 状态“S_IDLE”空闲状态，收到读写寄存器请求写迚入“S_CE_HIGH”状态，将 CE 拉高，然 后根据请求类型，迚入读（S_READ）戒写状态(S_WRITE)。 “S_WRITE”状态下一个状态迚入写地址状态“S_WRITE_ADDR”,再迚入写数据状态 “S_WRITE_DATA”，完成一个寄存器的写入，最后应答，拉低 CE。 “S_READ”状态下一个状态迚入读地址状态“S_READ_ADDR”,再迚入读数据状态 “S_READ_DATA”，完成一个寄存器的读取，最后应答，拉低 CE。 module top( //sys input clk, input rst_n, output rtc_sclk, output rtc_ce, inout rtc_data, input uart_rx, output uart_tx ); wire[7:0] read_second; wire[7:0] read_minute; wire[7:0] read_hour; wire[7:0] read_date; wire[7:0] read_month; wire[7:0] read_week; wire[7:0] read_year; ds1302_test ds1302_test_m0( .rst (~rst_n), .clk (clk), .ds1302_ce (rtc_ce), .ds1302_sclk (rtc_sclk), .ds1302_io (rtc_data), .read_second (read_second), .read_minute (read_minute), .read_hour (read_hour), .read_date (read_date), .read_month (read_month), .read_week (read_week), .read_year (read_year) ); uart_send uart_send_m0( .clk (clk ), .rst_n (rst_n ), .read_second (read_second ), .read_minute (read_minute ), .read_hour (read_hour ), .read_date (read_date ), .read_month (read_month ), .read_week (read_week ), .read_year (read_year ), .uart_rx (uart_rx ), .uart_tx (uart_tx ) );

Cyclone2 FPGA读写SRAM IS61LV25616 实验Verilog逻辑源码Quartus工程文件 module SRAM_TEST ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output inout [15:0] SRAM_DQ , output reg [17:0] SRAM_ADDR , output reg SRAM_CE , output reg SRAM_OE , output reg SRAM_WE , output reg SRAM_UB , output reg SRAM_LB , output reg [ 7:0] LED ); //Reg define reg [3:0] div_cnt ; reg sram_clk ; reg [5:0] ctrl_cnt ; reg [15:0] sram_data_lck ; reg [15:0] sram_din ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to sram ctrl clk 50M/16 always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 4'b0; else div_cnt <= div_cnt + 4'b1; end //gen sram_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) sram_clk <= 1'b0 ; else if ( div_cnt <= 4'd7 ) sram_clk <= 1'b1 ; else sram_clk <= 1'b0 ; end // sram ctrl signal gen // ctrl_cnt 0 - 31 is for write ctrl // ctrl_cnt 31 - 63 is for read ctrl always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 6'b0; else ctrl_cnt <= ctrl_cnt + 6'b1; end always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) SRAM_ADDR <= 18'b0; else if ( ctrl_cnt

Cyclone2 FPGA读写FLASH SST39VF1601 实验Verilog逻辑源码Quartus工程文件 module FLASH_TEST ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output inout [15:0] FLASH_DQ , output reg [20:0] FLASH_ADDR , output reg FLASH_CE , output reg FLASH_OE , output reg FLASH_WE , output reg FLASH_RST , output reg [ 7:0] LED ); //Reg define reg [3:0] div_cnt ; reg flash_clk ; reg [31:0] wait_cnt ; reg [5:0] ctrl_cnt ; reg [15:0] flash_data_lck ; reg [15:0] flash_din ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to flash ctrl clk 50M/16 , one flash ctrl clk cycle is 330ns always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 4'b0; else div_cnt <= div_cnt + 4'b1; end //gen flash_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) flash_clk <= 1'b0 ; else if ( div_cnt <= 4'd7 ) flash_clk <= 1'b1 ; else flash_clk <= 1'b0 ; end // flash ctrl signal gen // read FLASH devid need 5 step : // ctrl_cnt 10 - 13 is write oxaa in addr 0x5555 // ctrl_cnt 14 - 17 is write ox55 in addr 0x2aaa // ctrl_cnt 18 - 21 is write ox90 in addr 0x5555 // ctrl_cnt 22 -30 is wait time for TIDA // ctrl_cnt 31 -34 is read manId in addr 0 // ctrl_cnt 35 -38 is read devid in addr

Cyclone2 FPGA读写DAC_TLC5620实验Verilog逻辑源码Quartus工程文件 module DA_TLC5620 ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output output reg DA_IO_CLK , output reg DA_LOAD , output reg DA_LDAC , output reg DA_OUT_DATA , output reg [7:0] LED ); //Reg define reg [6:0] div_cnt ; reg da_clk ; reg [4:0] ctrl_cnt ; reg [15:0] delay_cnt ; reg [ 7:0] analog_data ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to da ctrl clk 50M/64 = 0.78Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 6'b0; else div_cnt <= div_cnt + 6'b1; end //gen da_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) da_clk <= 1'b0 ; else if ( div_cnt <= 6'd31 ) da_clk <= 1'b1 ; else da_clk <= 1'b0 ; end // da ctrl signal gen // ctrl_cnt 0 - 32 is for da ctrl always @(posedge da_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 5'b0; else ctrl_cnt <= ctrl_cnt + 5'b1; end always @(posedge da_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_IO_CLK <= 1'b0; else if ( ctrl_cnt == 5'd6 || ctrl_cnt == 5'd8 || ctrl_cnt == 5'd10 || ctrl_cnt == 5'd12 || ctrl_cnt == 5'd14 || ctrl_cnt == 5'd16 || ctrl_cnt == 5'd18 || ctrl_cnt == 5'd20 || ctrl_cnt == 5'd22 || ctrl_

Cyclone4 FPGA读写高速AD-TLC549+DA-AD9708模块实验Verilog逻辑源码Quartus工程+文档资料 module DA_AD9708_BASE ( //input input sys_clk , //system clock; // input sys_rst_n , //system reset, low is active; input [3:0] key , //output output reg [7:0] DA_DATA , output reg DA_CLK , output reg [7:0] LED ); //Reg define reg [7:0] div_cnt ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ assign sys_rst_n = 1'b1 ; // counter used for div osc clk to ad ctrl clk 50M/4 = 12.5Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 8'b0; else div_cnt <= div_cnt + 8'b1; end //gen DA_CLK always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_CLK <= 1'b0 ; else if ( div_cnt == 8'd0 ) DA_CLK <= ~DA_CLK ; else ; end //display AD sample data to LED always @(posedge DA_CLK or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_DATA <= 8'b0; else DA_DATA <= { key, key }; end //display AD sample data to LED always @(posedge DA_CLK or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) LED <= 8'b0; else LED <= { key, key } ; end

Cyclone2 FPGA读写 ADC_TLC549实验Verilog逻辑源码Quartus工程文件, module AD_TLC549 ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; input AD_IO_DATA , //output output reg AD_IO_CLK , output reg AD_CS , output reg [7:0] LED ); //Reg define reg [6:0] div_cnt ; reg ad_clk ; reg [4:0] ctrl_cnt ; reg [7:0] ad_data_shift ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to ad ctrl clk 50M/64 = 0.78Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 6'b0; else div_cnt <= div_cnt + 6'b1; end //gen ad_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ad_clk <= 1'b0 ; else if ( div_cnt <= 6'd31 ) ad_clk <= 1'b1 ; else ad_clk <= 1'b0 ; end // ad ctrl signal gen // ctrl_cnt 0 - 32is for ad ctrl always @(posedge ad_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 5'b0; else ctrl_cnt <= ctrl_cnt + 5'b1; end always @(posedge ad_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) AD_IO_CLK <= 1'b0; else if ( ctrl_cnt == 5'd6 || ctrl_cnt == 5'd8 || ctrl_cnt == 5'd10 || ctrl_cnt == 5'd12 || ctrl_cnt == 5'd14 || ctrl_cnt == 5'd16 || ctrl_cnt == 5'd18 || ctrl_cnt == 5'd20 ) // ad clk low AD_IO_CLK <= 1'b1; else AD_IO_CLK <= 1'b0; end always @(posedge ad_clk or negedge sys_rst

FPGA控制LCD12864显示屏显示图片实验Verilog逻辑源码Quartus11.0工程文件, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 ​ module LCD12864(clk,rst,lcd12864_rs,lcd12864_rw,lcd12864_en,lcd12864_data,psb); input clk; //系统时钟 input rst; //复位信号 output lcd12864_rs; //1:数据模式;0:指令模式 output lcd12864_rw; //1:读操作;0:写操作 output lcd12864_en; //使能信号,写操作时在下降沿将数据送出;读操作时保持高电平 output psb; output[7:0] lcd12864_data; //LCD数据总线 reg lcd12864_rs; reg lcd12864_en; reg[7:0] lcd12864_data; reg[3:0] state; //状态机 reg[3:0] next_state; reg[14:0] div_cnt; //分频计数器 reg[9:0] cnt; //写操作计数器 reg cnt_rst; //写操作计数器复位信号 wire[7:0] data; //要显示的数据 reg clk_div; //分频时钟 /********************状态机参数*********************/ parameter idle = 4'b0000, setbase_1 = 4'b0001, setmode_1 = 4'b0010, setcurs_1 = 4'b0111, setexte_1 = 4'b0100, setexte_2 = 4'b1100, wr_y_addr_1 = 4'b1101, wr_y_addr_2 = 4'b1111, wr_x_addr_1 = 4'b1110, wr_x_addr_2 = 4'b1010, wr_data_1 = 4'b1011, wr_data_2 = 4'b1001; assign lcd12864_rw = 1'b0; //对LCD始终为写操作 assign psb=1'b1; //开背光灯 /******************时钟分频**********************/ always @(posedge clk or negedge rst) begin if(!rst) div_cnt <= 15'd0; else if(div_cnt==15'h4000) begin div_cnt <= 15'd0; clk_div<=~clk_div; end else div_cnt <= div_cnt+ 1'b1; end /**************状态机转向*********/ always @(posedge clk_div or negedge rst) begin if(!rst) state <= idle; else state <= next_state; end /***************************************************************/

FPGA控制LCD12864显示屏显示4行字符实验Verilog逻辑源码Quartus11.0工程文件，, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 module lcd12864(clk,rs,rw,en,dat,psb); input clk; //系统时钟输入50M output [7:0] dat; //LCD的8位数据口 output rs,rw,en,psb; //LCD的控制脚 reg e; reg [7:0] dat; reg rs; reg [15:0] counter; reg [6:0] current,next; reg clkr; reg [1:0] cnt; ///////////////////////////////////////////// assign psb=1'b1; assign rw=0; always @(posedge clk) //da de shi zhong pinlv begin counter=counter+1; if(counter==16'h000f) clkr=~clkr; end //////////////////////////////////////////////// always @(posedge clkr) begin current=next; case(current) 7'd0: begin rs<=0; dat<=8'h31; next<=next+1'b1;end //*设置8位格式,* 7'd1: begin rs<=0; dat<=8'h0C; next<=next+1'b1;end //*整体显示,关光标,不闪烁*/ 7'd2: begin rs<=0; dat<=8'h06; next<=next+1'b1; end //*设定输入方式,增量不移位*/ 7'd3: begin rs<=0; dat<=8'h01; next<=next+1'b1; end //*清除显示*/ 7'd4: begin rs<=1; dat<=8'hB4; next<=next+1'b1; end //显示第一行 7'd5: begin rs<=1; dat<=8'hF3; next<=next+1'b1; end 7'd6: begin rs<=1; dat<=8'hCE; next<=next+1'b1; end 7'd7: begin rs<=1; dat<=8'hF7;next<=next+1'b1; end 7'd8: begin rs<=1; dat<=8'hB9; next<=next+1'b1; end 7'd9: begin rs<=1; dat<=8'hCF; next<=next+1'b1; end 7'd10: begin rs<=1; dat<="-"; next<=next+1'b1; end 7'd11: begin rs<=1; dat<="F";next<=next+1'b1; end 7'd12: begin rs<=1; dat<="P"; next<=next+1'b1; end 7'd13: begin rs<=1; dat<="G";next<=next+1'b1; end 7'd14: begin rs<=1; dat<="A"; next<=next+1'b1; end 7'd15: begin rs<=1; dat<="!"; next<=next+1'b1; end 7'd16: begin

cyclone4 FPGA读写8位AD转换器TLC549实验Verilog逻辑源码Quartus11.0工程文件, FPGA型号为EP4CE6E22C8,可以做为你的学习设计参考。 ( clk, //系统50MHZ时钟 adc_sclk, //AD TLC549的时钟 data, //AD TLC549的数据口 cs, //AD TLC549的片选择 wei, //数码管的为选择 duan //数码管的7段码 ); input clk; input data; output cs; output adc_sclk; output[7:0] duan; output[3:0] wei; reg cs,adc_sclk,clk1k,clk1ms; reg[15:0] count; reg[24:0] count1ms; reg[3:0] cnt; reg[2:0] number; reg[1:0] state; reg[3:0] wei; reg ledcs; reg [7:0] duan; reg[7:0] dataout; reg[16:0] tenvalue; parameter sample=2'b00, display=2'b01; /**********产生100k的采集时钟信号*********/ always@(posedge clk) begin if(count<=250) count<=count+1'b1; else begin count<=0; adc_sclk25'd25000) begin clk1ms<=~clk1ms; count1ms<=0; end else count1ms<=count1ms+1; end /*********AD采样程序**************/ always@(negedge adc_sclk) begin case(state) sample: begin cs<=0; dataout[7:0]4'd7) begin cnt<=0; state<=display; end else begin cnt<=cnt+1; state<=sample; end end display: begin cs<=1;//关AD片选 tenvalue>4)&8'b0000_1111)*16+ tendata(dataout&8'b0000_1111))*129;// //得到采集的数据 state<=sample; end default: state<=display; endcase end /***********2进制转十进制函数*************/ function[7:0] tendata;//返回一个4位的数字 input[7:0] datain; begin case(datain) 4'b00000000: tendata=4'd0;//0 4'b00000001: te

cyclone4 FPGA读写DAC芯片TLC5615实验Verilog逻辑源码Quartus11.0工程文件, FPGA型号为EP4CE6E22C8,可以做为你的学习设计参考。 module TLC5615_display (clk, //�ڲ�ʱ�� sclk, //TLC5615 sclkʱ�ӽ� din, //TLC5615 din���ݽ� cs); //TLC5615 csƬѡ input clk; output din; output cs; output sclk; reg din; reg cs; reg sclk; reg[3:0] count1,count2,count3; reg[9:0] din_reg; //10λ���ݼĴ��� initial //��ʼ�� begin cs=1; din=0; count1=0; count2=0; count3=0; din_reg=10'd250; //ʵ���߿��Ը�����Ҫ�޸�10Ϊ�������� end /*** sclk��Ƶ������Ϊ2.5MHz ***/ always@(posedge clk) begin if(count3==4'd9) begin sclk<=~sclk; count3<=0; end else count3=4'd12&&count1<4'd15) begin cs<=1; //���Ƭѡ count1<=count1+4'd1; end else if(count1==4'd15) begin count1<=0; end else begin cs<=0;