Altera Cyclone 全系列原理图库+PCB封装库(AD集成库),.IntLib后缀文件,拆分后文件为PcbLib+SchLib格式,Altium Designer原理图库+PCB封装库,集成库型号列表如下: Library Component Count : 144 Name Description ---------------------------------------------------------------------------------------------------- EP1C12F256C6 Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 6 EP1C12F256C6N Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 6, Pb-Free EP1C12F256C7 Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 7 EP1C12F256C7N Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 7, Pb-Free EP1C12F256C8 Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 8 EP1C12F256C8N Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 8, Pb-Free EP1C12F256I6 Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Industrial Grade, Speed Grade 6 EP1C12F256I6N Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Industrial Grade, Speed Grade 6, Pb-Free EP1C12F256I7 Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Industrial Grade, Speed Grade 7 EP1C12F256I7N Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Industrial Grade, Speed Grade 7, Pb-Free EP1C12F256I8 Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Industrial Grade, Speed Grade 8 EP1C12F256I8N Cyclone Family, 1.5V FPGA, 185 I/O Pins, 2 x PLLs, Industrial Grade, Speed Grade 8, Pb-Free EP1C12F324C6 Cyclone Family, 1.5V FPGA, 249 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 6 EP1C12F324C6N Cyclone Family, 1.5V FPGA, 249 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 6, Pb-Free EP1C12F324C7 Cyclone Family, 1.5V FPGA, 249 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 7 EP1C12F324C7N Cyclone Family, 1.5V FPGA, 249 I/O Pins, 2 x PLLs, Commercial Grade, Speed Grade 7, Pb-Free EP1C12
Altera Cyclone II 全系列原理图库+PCB封装库(AD集成库).IntLib后缀文件,拆分后文件为PcbLib+SchLib格式,Altium Designer原理图库+PCB封装库,集成库型号列表如下: Library Component Count : 234 Name Description ---------------------------------------------------------------------------------------------------- EP2C15AF256C6 Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 6, Commercial Grade EP2C15AF256C6N Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 6, Commercial Grade, Pb-Free EP2C15AF256C7 Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 7, Commercial Grade EP2C15AF256C7N Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 7, Commercial Grade, Pb-Free EP2C15AF256C8 Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial Grade EP2C15AF256C8N Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Commercial Grade, Pb-Free EP2C15AF256I6 Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 6, Industrial Grade EP2C15AF256I6N Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 6, Industrial Grade, Pb-Free EP2C15AF256I7 Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 7, Industrial Grade EP2C15AF256I7N Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 7, Industrial Grade, Pb-Free EP2C15AF256I8 Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Industrial Grade EP2C15AF256I8N Cyclone II Family, 1.2V FPGA, 152 I/O Pins, 2 PLLs, 256-Pin FBGA, Speed Grade 8, Industrial Grade, Pb-Free EP2C15AF484C6 Cyclone II Family, 1.2V FPGA, 315 I/O Pins, 4 PLLs, 484-Pin FBGA, Speed Grade 6, Commercial Grade EP2C15AF484C6N Cyclone II Family, 1.2V FPGA, 315 I/O Pins, 4 PLLs, 484-Pin FBGA, Speed Grade 6, Commercial Grade, Pb-Free EP2C15AF4
altera的EP4SGX70控制国产的250M采样率的AD CL3449 源程序
2021-04-09 09:00:34 55.05MB altera的EP4SGX70控 250M采样率的AD ADCL3449
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Altera FPGA pcie MSI中断驱动 ,也可用于其它带pcie接口的FPGA中断功能开发。
2021-04-08 20:49:47 7KB fpga  pcie msi
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使用Verilog编写的用Altera FPGA的串口屏(HMI)控制源码,内部已包含有数据转换的部分,可直接用于将对应数据显示,还可以用于串口发送字符串等其他操作,并且包含有串口屏数据输入的读取,代码风格清晰。
2021-04-07 20:44:42 4.85MB Verilog FPGA HMI USART
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小梅哥AC6102开发板原理图,板载DDR2,USB3.0,千兆以太网
2021-04-07 10:13:36 540KB altera FPGA
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适合win10的usb-blaster驱动程序
2021-04-03 17:02:48 811KB 驱动程序
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Altera最新Timequest时序分析高级培训教材
2021-04-03 10:39:19 1.87MB 时序分析
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数字通信同步技术的MATLAB与FPGA实现 Altera Verilog版 [杜勇 编著] 2015年
2021-04-02 21:26:03 49.4MB Altera Verilog
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利用DDS技术的调制特性生成BPSK信号,只需控制DDS的相位控制字P,让其随调制信号进行变化即可。当调制信号为“0”时,载波相位为0,即相位控制字P为0;当调制信号为“1”时,载波相位为π,即相位控制字P为512。这样,通过相位累加器的输出与受控相位控制字P相加,就可得到DDS中ROM的寻址地址,从而进一步生成BPSK信号。
2021-04-01 11:32:58 43.71MB Altera FPGA Verilog BPSK
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